The LE/FT lab has some experience with analog translinear circuit design, having spent several years investigating analog decoders and subthreshold circuits for implementing Bayesian inference with applications in forward error correction. One of the major difficulties with subthreshold analog computation is that the circuits require well-balanced differential signal processing. This balance is upset by *device mismatch*, an inevitable consequence of manufacturing. Although our research has largely moved away from current-mode subthreshold processing, we recently proposed a novel mismatch-tolerant circuit approach based on the CMOS double-pair topology. Gopal Sundar used this approach to develop an improved winner-take all (WTA) circuit, as described in his recent MWSCAS article. This blog post presents the basic theory of the CMOS double-pair, its application in translinear computation, and its comparative sensitivity to mismatch.

First, the CMOS double-pair is an arrangement in which an NMOS device is positioned above a PMOS device like this:

If both of the devices are biased in weak inversion, then their behavior is approximated by these device equations:

\( \begin{align*} i_{DN} &= I_{0N} \exp\left(\frac{v_{g1}-v_s}{nU_T}\right)\\ i_{DP} &= I_{0P} \exp\left(\frac{v_s - v_{g2}}{nU_T}\right) \end{align*} \)

where $U_T$ is the thermal voltage ($k_BT/q$) and $n$ is the subthreshold slope parameter (near 1). (In this post we neglect a body effect parameter and other model details that complicate the analysis). Since $i_{DN} = i_{DP}$, we can eliminate $v_s$:

$ i_D = \sqrt{I_{0N}I_{0P}} \exp\left(\frac{v_{g1} - v_{g2}}{nU_T}\right). $

At this point it is somewhat customary to declare that all currents have units of $ \sqrt{I_{0N}I_{0P}}$ and all voltages have units of $nU_T$. Then the CMOS double-pair is characterized by the simplified equation

$ i_D = \exp\left(v_{g1} - v_{g2}\right).$

From here we can directly apply the translinear principle, which allows us to create interesting combinations of current multiplication, division, squaring and square-root circuits that have been popular for implementing analog neural networks and other non-linear signal processing circuits, particularly in the Computation and Neural Systems community. As a basic example, it is possible to multiply currents because of the exponential law:

$ \prod_k i_{Dk} = \sum_k \left(v_{g1}-v_{g2}\right)_k $

By manipulating this law, we can produce various arrangements of the gate connections to achieve the aforementioned functions.

This blog post will not go into the possible translinear applications of the CMOS double pair. Instead we will focus just on the circuit's mismatch tolerance. If we consider only the effect of $V_T$ variation (i.e. threshold voltage variation) in the NMOS device, we have the following small-signal behavior:

\( \begin{align*} v_s &= v_{g1}\left(\frac{g_{mn}r_{on}}{1+g_{mn}r_{on}}\right) \\ \textrm{and}~ i_d &= g_{mn}\left(v_{g1}-v_s\right) \end{align*} \)

The sensitivity to mismatch is approximately given by the ratio $i_d/v_{g1}$, so

\( \begin{align*} \frac{i_d}{v_{g1}} &= \frac{g_{mn}}{1+g_{mn}r_{on}} \end{align*} \)

For the PMOS device, an identical analysis applies. Because mismatch is a random process, we may model it via a random variable $\epsilon$, so that the threshold voltage of device $i$ is

${V_T}_i = V_{T0}\left(1 + \epsilon_i\right)$

If $\epsilon$ has variance $\sigma_\epsilon^2$, then the total mismatch variance in $i_d$ is equal to

\( \begin{align*} \sigma_i^2 &= \sigma_\epsilon^2 \left[\left(\frac{g_{mn}}{1+g_{mn}r_{on}}\right)^2 + \left(\frac{g_{mp}}{1+g_{mp}r_{op}}\right)^2\right] \end{align*} \)

We may directly compare this to the total mismatch variation seen in a single MOSFET device. Since $v_s$ doesn't vary in a typical translinear circuit, the current is directly proportional to the $V_T$ fluctuation, hence:

\(\begin{align*} \sigma_i^2~\textrm{(single MOSFET)} &= \sigma_\epsilon^2 g_{m}^2 \end{align*}\)

Therefore if $g_m r_o$ is large, then the mismatch sensitivity is greatly reduced in the double pair circuit, with the final variance being diminished by a factor of $\left(1+g_m r_o\right)^2$. We believe this explains the improved mismatch characteristics that were observed in Monte Carlo simulation results described in our MWSCAS paper. There are still major limitations to using CMOS double-pair circuits, especially that they require a higher supply voltage to operate correctly. This fact makes it unlikely to realize double-pair translinear circuits in advanced technologies with feature size below 100nm. It may be argued that many applications do not require nano-scale fabrication; micron-scale translinear circuits may still be attractive for some applications based on a computation per watt per dollar evaluation. In that case, the double-pair may be considered an incremental contribution for improving the characteristics of those circuits.

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