The LE/FT lab has some experience with analog translinear circuit design, having spent several years investigating analog decoders and subthreshold circuits for implementing Bayesian inference with applications in forward error correction. One of the major difficulties with subthreshold analog computation is that the circuits require well-balanced differential signal processing. This balance is upset by device mismatch, an inevitable consequence of manufacturing homepage. Although our research has largely moved away from current-mode subthreshold processing, we recently proposed a novel mismatch-tolerant circuit approach based on the CMOS double-pair topology. Gopal Sundar used this approach to develop an improved winner-take all (WTA) circuit, as described in his recent MWSCAS article. This blog post presents the basic theory of the CMOS double-pair, its application in translinear computation, and its comparative sensitivity to mismatch.